Measurement-Based Extraction of MOSFET Small-Signal Parameters

In this report, a parameter extraction procedure and a model presented in [4] are tested using a 280×0.25μm transistor manufactured in a 0.25 μmCMOS process. The extraction procedure is based on two sets of S-parameter measurements. The first transistor measurement is in the linear region, to obtain the extrinsic terminal resistances which are biasindependent . The intrinsic parameters of the transistor are found using measurements of the transistor in saturation. The gate-drain and gate-source capacitances, along with the gate/ back-gate transconductances and output conductance are extracted directly. These are subsequently deembedded from the measurements to obtain the bulk admittance. Finally, the source-bulk and drain-bulk capacitances and the bulk resistance network are optimized to fit the measurements. The method compares favourably with measurements, apart from the estimate of the gate-resistance, which is too high. By replacing this with the gate-resistance estimate in [5], the fit improves significantly. The channel delay factor included in the model is necessary to model forward transmission accurately at higher frequencies. THE extraction of small-signal parameters of MOSFETs is of great interest to RF circuit designers. However, as the MOSFET is influenced by bulk effects at gigahertz frequencies, direct measuring-based extraction is quite complicated. In a recent paper [4], an approach was suggested which links common-source MOSFET measurements to a small-signal RF model which is valid up to the cutoff frequency. While a quasi-static assumption does not hold to frequencies above fT/3 [9], the proposed method increases the the scope of applicability by introducing a delay in conjunction with the transconductance. For recent submicron CMOS processes (sub-0.25μm) this should give a valid frequency range up to around 8-12GHz which is sufficient in many situations. In this report, the proposed extraction procedure is described and it’s applicability is demonstrated by use of MOSFETs fabricated in a 0.25μm CMOS technology. 1 BASIC MODEL DESCRIPTION The employed small-signal RF MOSFET model is shown in Figure 1. Note that the non-quasistatic effects have been partially incorporated in the three generators by the channel delay factor τ . These generators represent the operation dependencies of gate-source, source-bulk, and drain-source voltages. Note, that all equations refer to the intrinsic gate, source, bulk, and Technical Report R2000-1004 , August 2000. RF Integrated Systems & Circuits (RISC) group, Aalborg University, Denmark. drain nodes. Hence, Vgsi is the voltage from intrinsic gate to intrinsic source (marked as “gi” and “si” in Figure 1) and Vgs denotes the voltage from the extrinsic gate and source nodes which are accessible by the designer.